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It exploits the parameters of SDR cores in order to integrate these existing library cores in the compilation flow hence enabling rapid prototyping of FPGA-based SDR at high-level of design abstraction. It is designed around use by both the novice and experienced low-level HDL developers, providing novice users with experience of using IP cores that support open bus interfaces in order to exploit System-On-Chip SoC design without commercial, parameter, and bus compatibility limitations.

The provided modules will be of particular benefit to the novice developers in providing ready-made examples of processing blocks, as well as parameterization settings for the interfacing cores and associated RF receiver side configuration settings. The remainder of this paper is organized as follows. Next, the existing IP libraries are reviewed in Section 3. The ever increasing popularity and evolution of wireless communication technologies and standards are changing the manner in which wireless services and applications are used [ 6 ].

The demand and usage of these services by users are growing rapidly and are constantly pushing designs to their limits. Wireless devices are becoming more common and users are demanding the convergence of multiple services and technologies [ 7 ] in a single device. These lead to potential challenges in areas of equipment design, wireless service provision, security, and regulation [ 8 ].

These types of technologies are upgradable, reconfigurable, and adaptable to changes in technology standards and need [ 9 ]. One such technology that offers all these features is SDR. SDR is defined as radio in which hardware components or physical layer functions of a wireless communications system are all implemented in software [ 10 ]. SDR prototyping has opened doors to many possibilities in the field of radio communications.

Owing to its rapid growth in recent years, it has gained popularity and has also found wide adoption in the analysis and implementation of many wireless communications systems. Traditional systems are now replaced by SDR systems because of their high reconfigurability and increased capabilities which suit modern wireless communications technology [ 9 , 10 ]. SDR relies on a general purpose hardware that is easy to program and configure in software to enable a radio platform to adapt to multiple forms of operation such as multiband, multistandard, multimode, multiservice, and multicarrier [ 6 , 10 ].

A typical SDR transceiver is depicted in Figure 1. This is also where signal preconditioning and postconditioning using analog functions such as amplification and heterodyne mixing prior to ADC and after the DAC take place [ 6 , 8 ]. The DSP performance largely depends on the digital computing hardware device used. Furthermore, improved and higher sampling ADCs and DACs are pushing the tasks traditionally performed in analog closer towards the antenna, hence allowing them to be processed digitally using processors or reconfigurable devices [ 11 ]. However, a drawback is that the ADCs and DACs are usually costly, and achieving high sampling rates over millions of samples per second remains a limitation in SDR [ 6 ]; this is a motivating factor for reusable SDR platforms for prototyping to share the cost of the same platform across multiple projects.

FPGAs are made of highly reconfigurable and multiple logic blocks and cells together with switch matrix to route signals between them [ 12 ]. Their flexibility and speed have made them popular and are preferred to lay a general purpose hardware platform for SDR.

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The reconfigurable and parallel characteristics of FPGAs enable computationally intensive and complex tasks to be processed in real time with better performance and flexibility. These features have seen them gaining popularity over traditional general purpose processors GPPs and DSP processors [ 10 ]. For these reasons, they are used in RC as their structure can be reconfigured during start-up or runtime to perform advanced computations [ 13 ]. FPGAs have led to the concept of design for reuse which is a driving factor in enhancing the productivity and improving the system-level design in SDR applications.

A library of parameterizable FPGA cores makes a design for reuse effective [ 14 ].

The timing, area, and power configurations are the key to SoC success as they allow mix-and-match of different IP cores so that the designer can apply the trade-offs that best suit the needs of the target application [ 15 ]. The continuous design and implementation of a library of HDL cores, called IP cores in this paper, is increasingly driven by the desire to meet shortest possible time-to-market. This has led to greater demands of minimal development and debugging time [ 14 , 16 ]. Many of the IP libraries have one or more of the characteristics listed below [ 14 , 16 — 19 ]: Hardware designers are relying on predesigned IP cores from the IP libraries to increase productivity and reduce design time.

A static IP does not allow high performance to be achieved even when hardware resources or power budget is available nor does it achieve better performance to save both size and power consumption [ 18 ]. Integrating the third-party IPs can also be a challenge. It is often time-consuming and error-prone [ 19 ]. The IP libraries developed by private vendors are expensive and prohibitive to low-cost prototyping [ 20 ]. All the above shortcomings of private vendor IP libraries have led to new open-source hardware development models where reusable IPs are developed and made freely available to the public.

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OpenCores has the considerable number of IPs as well as Wishbone bus and its cores are accessible for free; however, OpenCores IPs are not parameterizable [ 20 ]. The methodology we followed in this project comprises the following four aspects: Decide a suitable design and interfacing scheme for this set of SDR cores based on input from expert consultants. Developing a comprehensive SDR application from the SDR cores and testing this application on hardware to validate the operation of the cores working together. Benchmarking the SDR core library to ensure these cores are of an adequate standard in comparison to similar IP cores available in other libraries.

The first step involved consultation with SDR experts. We interviewed and corresponded with these experts involved in FPGA-based design and implementation, both from industry and academia. Members of the engineering team at the Square Kilometre Array SKA were corresponded with in order to gain suggestions and feedback related to designs, processing requirements, and interfacing techniques; a total of three staff members contributed insights.

We also met and corresponded with researchers involved with FPGA work at the University of Cape Town, including research scientists, postgraduate researchers, research officers, and academic staff; insights from four senior researcher staff and three postgraduate researchers were obtained at the university. The insights gained from this process were then used to prepare the design for the SDR core library and to decide the parameters that the cores should provide.

During the second step, testing of the individual cores was done to validate their operation; this was done using simulation and test vectors and by running the cores on a hardware platform. As part of this step, a reconfigurable hardware platform was chosen on which to test the cores. The chosen platform contained an FPGA that connected directly to a high-speed sampling card and to an Ethernet port for sending data. The results of this testing are shown in Section 6. In the third step, we developed a representative SDR application that used the cores to confirm their operation and adequate performance when integrated as part of a complete SDR system.

This application involved the development of an FM receiver for which digitally downconverted data was transferred over Ethernet to a host computer for demodulation and playback. In the fourth step, our SDR cores were benchmarked against alternate cores available from other libraries. This benchmarking was done to confirm that the cores did not utilize an excessive number of logic elements compared to alternate solutions and that the operational clock rates of our cores were at adequate speed.

Section 8 reports the benchmarking results.

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The proposed DSL and supporting tool-chain is presented in Section 9. For the design of DSP cores, we follow a modular coding approach using technology-independent logic elements which result in simple and reusable functional blocks. Many commercial cores are closed source, licensed modules provided as monolithic hardware routing implementations optimized for and compatible with specific FPGA chips. A benefit of our cores is the availability of the underlying source code and therefore can be customized and be optimized further to meet the design requirements. Novice developers wanting to reuse these processing cores would consequently be advised to review the theoretical operation of the cores, possibly trying them in Octave or Matlab to gain a practical understanding of their behavior or limits, whereafter they would be familiar with the parameters concerned and be well prepared for moving to the FPGA, RHINO-based context of application of making these processing operations work in real time.

The design of the DSP cores presented in this paper is influenced by previous work performed for the design of hardware architectures to implement DSP algorithms. Wishbone bus slave interfaces were added to these designs to accommodate reusability, considering that the Wishbone standard is commonly used by developers making use of open-source or open-hardware IP. Some of these DSP algorithms have been used by both commercial and open-source IP designers to implement their IP cores; however obtaining optimal results depends on the RTL coding style at a low level of design abstraction; thus the commercial solutions, in particular, are likely to have significant optimization performed for their proprietary implementations.

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Commercial IP cores are typically optimized for deployment on specific platforms whereas the open-source community hardly follows similar levels of consistency and standardization needed to implement such high-quality designs. In this work, we pay much attention to good RTL design conventions and practices typically obtained from consultation with experts and our own experience in FPGA design.

All these design practices and many others not mentioned above make the optimization by low-level synthesis tools easier and effective. We also parameterize the cores to make it possible for future integration in the high-level synthesis tools. The general structure of the design of the DSP cores is shown in Figure 2. In this project, only restricted selection of IP cores was developed due to time constraint. These were chosen specially in consideration of common SDR processing needs and was also based on a thorough literature review as well as establishing priorities on what was needed for RHINO platform.

During the production test, Xilinx recommends that you re-examine the working range at corner case operating conditions to determine whether any final adjustments to the final phase-shift setting are needed. Page of Go. Introduction Page 20 - Specifications Page 21 - Chapter 2: Designing with the Core Page 36 - Figure Using the Client Side Data Pa Flow Control Implementation Page 60 Page 61 - Chapter 7: Using the Physical Side Inter Page 62 - Figure Page 69 - Figure Page 72 Page 73 - Figure Page 74 - Figure Configuration and Status Page 81 Page 82 - Chapter 8: Configuration and Status Page 83 Page 84 - Figure Configuration Register Write Page 85 - Figure Constraining the Core Page 94 - Chapter 9: Page 97 - Figure Page Page - Constraints when Implementing an Externa Page - Figure Page Page - Figure Page Page - Chapter Interfacing the Ethernet St Page Page Page - Chapter Core Verification, Complianc Page Page - Appendix C: Page Page - Appendix D: Table of Contents Add to my manuals Add.

Previous page. Next page. Xilinx virtex-ii pro embedded development platform user guide 70 pages. Xilinx inc. Reference system: Page 3: Page 5: Table Of Contents Page Page 8 Generating the Xilinx Netlist Page 9: Schedule Of Figures Figure Page 10 Figure Page 11 Figure A Schedule Of Tables Table Page 14 Table A Chapter 1: Introduction Xilinx.

Specifications For technical support, see support. Chapter 2: Core Interfaces Figure Chapter 3: Chapter 4: Designing With The Core The following sections discuss the design steps required for various implementations.

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Keep It Registered While registering signals may not be possible for all paths, it simplifies timing analysis and makes it easier for the Xilinx tools to place-and-route the design. Chapter 5: Page 46 Bit 26 reserved has been inserted into version 8. Vlan Tagged Frames Statistics core is used with the MAC, then accuracy cannot be guaranteed if the interframe gap adjustment is set to less than 12 idles.

Page 51 Broadcast Frame Asserted if the previous frame contained a broadcast address in the destination address field. Page 52 Bit 30 is equivalent to bit 20 of all previous core versions. Chapter 6: Flow Control Implementation Example MAC immediately resumes transmission it does not wait for the original requested pause duration to expire. Chapter 7: Page 64 DCM reset signal must be connected correctly: Either link synchronization has failed or Auto-Negotiation if present and enabled has failed to complete.

When auto-negotiation is enabled this signal is identical to Status Register Bit 1. Link Status.

Description

When low, synchronization has failed. Table 3: It is expected that this signal will be tied off to a logical value. Table 4: Reserved currently unused? Loopback Control When the core with a device-specific transceiver is used, this places the core into internal loopback mode.

With the TBI version, Bit 1 is connected to ewrap. When set to 1 this indicates to the external PMA module to enter loopback mode. A reset must be applied to clear. With the TBI version this bit is unused. The core is connected to the chosen transceiver in the HDL example design delivered with the core. For a complete description of the device-specific transceiver interface, see the transceiver User Guide specific to your device.

For User Guide information, see References [6], [7], and [8] at the end of this document. Table 5: Reset signal issued by the core to the device-specific transceiver transmitter path. A DCM may be used to derive userclk and userclk2. This is implemented in the HDL design example delivered with the core. The core will use this input to hold the device-specific transceiver in reset until the DCM obtains lock. Connects to transceiver signal of the same name. When the core is used with the device-specific transceiver, userclk2 is used as the MHz reference clock for the entire core.

Table 6: Tolerance must be within IEEE This signal is currently tied to Ground. Enables the PMA Sublayer to perform comma realignment. Table 7: The duration of this timer is set to the binary number input into this port multiplied by clock periods of the MHz reference clock 8 ns. This port is replaced when using the dynamic switching mode. Active high interrupt to signal the completion of an Auto-Negotiation cycle.

Table 8: Used as the reset default to select the standard. It is expected that this signal will be tied off to a logical value: